A MOS transistor comprises a parasitic capacitance between a drain of the MOS transistor and a gate of the MOS transistor, and also between a source of the MOS transistor and the gate of the MOS transistor. Sometimes, the parasitic capacitance limits a speed at which a device comprising the MOS transistor can operate. Sometimes, the parasitic capacitance can cause a memory device comprising the MOS transistor to read incorrect data.
Sometimes, the effects of the parasitic capacitance are inhibited by connecting a capacitor to the gate of the MOS transistor.